Research Collaborations

Professor: Sahar HOTEIT, Hela MAROUANE, Abdulhalim DANDOUSH – PhD Student: Rim SAYEGH

• Title: Optimizing Joint Radio and Computing Resource Allocation in Vehicular Edge Computing.
• Abstract: This PhD thesis focuses on enhancing Intelligent Transportation Systems (ITS) by integrating Vehicular Edge Computing (VEC) into 5G networks to overcome the hardware limitations of individual vehicles. Since critical V2X services are highly sensitive to latency, the research leverages SDN and NFV technologies to process data at the network edge rather than in a distant cloud, thereby ensuring high bandwidth and rapid response times. The primary objective is to develop a joint resource allocation framework that efficiently manages both radio and computational resources to minimize the cumulative delay caused by transmission and processing.
• Keywords: Vehicular Communication Systems V2X, Vehicular Edge Computing (VEC), Resource Allocation.
• Establishment: Paris-Saclay University, Gif-sur-Yvette, France.
• Laboratory: Signals and Systems Laboratory (Research team: Telecommunications and Networks - CentraleSupélec).
• Doctoral school: Doctoral School of Information and Communication Sciences and Technologies.
• Duration: January 2026 - Present.

Professor: Laurent CLAVIER – PhD Student: Miled ALAM

• Title: Towards secrecy energy-efficient solutions for cooperative backscatter-aided non-orthogonal multiple access systems.
• Abstract: This PhD thesis investigates the enhancement of Physical Layer Security (PLS) and energy efficiency in next-generation wireless networks by combining NOMA with Ambient Backscatter Communication (AmBC). The study develops novel resource allocation strategies to maximize Secrecy Energy-Efficiency (SEE), providing exact mathematical solutions that simplify complex optimization problems into efficient, low-complexity searches. To address real-time dynamic environments, the project integrates Explainable Artificial Intelligence (XAI) to predict optimal allocations with high accuracy while ensuring model interpretability and significantly reduced computational overhead.
• Keywords: Non-Orthogonal Multiple Access (NOMA), Ambient Backscatter Communication (AmBC), Physical Layer Security (PLS), Energy Efficiency, Internet of Things (IoT), Explainable Artificial Intelligence (XAI).
• Establishment: IMT Nord Europe, Lille, France.
• Laboratory: Center for Education, Research and Innovation in Digital Systems (CERI-SN).
• Doctoral school: Doctoral School of Mathematics, Digital Sciences, and Their Interactions.
• Duration: June 2023 - August 2025.

Professor: Sumit J. DARAK – PhD Student: Syed Asrar Ul HAQ

• Title: Reconfigurable Deep Learning Augmented Channel Estimation for Vehicular Networks on System on Chip.
• Abstract: Reliable and fast channel estimation is crucial for next-generation wireless networks supporting a wide range of vehicular and low-latency services. Recently, deep learning (DL)-based channel estimation has been explored as an efficient alternative to conventional least-square (LS) and linear minimum mean square error (LMMSE) approaches. Most of these DL approaches have not been realized on system on chip (SoC), and preliminary study shows that their complexity exceeds the complexity of the entire physical layer (PHY). The high latency of DL is another concern. This article considers the design and implementation of deep neural network (DNN) augmented LS (LSDNN)-based channel estimation for preamble-based orthogonal frequency-division multiplexing (OFDM) PHY on SoC. We demonstrate the gain in performance compared with the conventional LS and LMMSE approaches. Via software–hardware codesign, word-length optimization, and reconfigurable architectures, we demonstrate the superiority of the LSDNN over LS and LMMSE for a wide range of signal-to-noise ratio (SNR), number of pilots, preamble types, and wireless channels. Furthermore, we evaluate the performance, power, and area (PPA) of the LS and LSDNN application-specific integrated circuit (ASIC) implementations in 45-nm technology. We demonstrate that word-length optimization can substantially improve PPA for the proposed architecture in ASIC implementations.
• Keywords: Channel Estimation, System on Chip (SoC), Software-Hardware Co-design.
• Establishment: Indraprastha Institute of Information Technology Delhi (IIIT-Delhi), New Delhi, India.
• Laboratory: Algorithms to Architecture (A2A) Research Lab.
• Duration: May 2021 - August 2025.